1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device.
2. Description of the Related Art
When a non-volatile memory device performs a read operation, data is outputted sequentially. For example, when a read command is first applied through an input/output pad and an address is applied, an address is counted from the applied address and the data stored in a page buffer corresponding to each address is sequentially outputted. Such a read operation is referred to as a serial read operation. Hereafter, a serial read operation of a non-volatile memory device is described.
FIG. 1 illustrates a conventional non-volatile memory device.
The non-volatile memory device shown in FIG. 1 includes a first bank 110 including a plurality of first page buffers A1 to AN, a second bank 120 including a plurality of second page buffers B1 to BN, and an address counter 130 that counts a first address ADD1<0:A> and a second address ADD2<0:A>.
Hereafter, the operation of the non-volatile memory device is described with reference to FIG. 1.
First, a read command is inputted to an input/output pad (not shown in FIG. 1) while a command latch enable (CLE) signal is enabled to a logic high level. Subsequently, an initial bank address BADD_INT, a page address, and a column address ADD_INT<0:A>are inputted to the input/output pad while an address latch enable (ALE) signal is enabled to a logic high level. The address counter 130 receives the initial bank address BADD_INT and the column address ADD_INT<0:A> while a load signal LOAD is enabled.
The initial bank address BADD_INT designates whether the data of the first bank 110 or the data of the second bank 120 is to be outputted during a multi-bank operation. The column address ADD_INT<0:A> indicates which page buffer from the multiple page buffers A1 to AN and B1 to BN of the banks 110 and 120 to output data. Also, the value of the first address ADD1<0:A> designates one page buffer among the multiple first page buffers A1 to AN, and the value of the second address ADD2<0:A> designates one page buffer among the multiple second page buffers B1 to BN.
Subsequently, a word line WLK designated by the page address is enabled. The data of a memory cell corresponding to the enabled word line WLK in a first memory array 111 is stored in the multiple first page buffers A1 to AN, and the data of a memory cell corresponding to the enabled word line WLK in a second memory array 121 is stored in the multiple second page buffers B1 to BN.
The non-volatile memory device performs a multi-bank operation, which means outputting the data stored in two or more banks, during a read operation. To perform the multi-bank operation, the address counter 130 counts a bank address BADD, the first address ADD1<0:A>, and the second address ADD2<0:A> from a time when the command latch enable (CLE) signal and the address latch enable (ALE) signal are enabled together. When the command latch enable (CLE) signal and the address latch enable (ALE) signal are enabled together is referred to as a first time, hereafter. The initial value of the bank address BADD is the initial bank address BADD_INT, and the initial values of the first address ADD1<0:A> and the second address ADD2<0:A> are both the column address ADD_INT<0:A>.
The bank address BADD is counted at a rising edge of a clock CLK. The data stored in the first page buffers between a starting first page buffer A3 and an ending first page buffer AN-1, which are designated by the column address ADD_INT<0:A> while the first address ADD1<0:A> is counted, are sequentially outputted at a rising edge of the bank address BADD. The data stored in the second page buffers between a starting second page buffer B3 and an ending second page buffer BN-1, which are designated by the column address ADD_INT<0:A> while the second address ADD2<0:A> is counted, are sequentially outputted at a falling edge of the bank address BADD.
In the conventional non-volatile memory device, the outputted data is stored in a plurality of pipe latches (not shown in FIG. 1) and outputted to a circuit outside of the non-volatile memory device through the input/output pad.
FIG. 2 is a waveform diagram illustrating the operation of the conventional non-volatile memory device.
After a command and an address are inputted through the input/output pad, a period for performing a read operation begins at a falling edge 201 of a ‘W/R#’ signal. Here, when the ‘W/R#’ signal is in a logic low level, it means a period for performing a read operation, and when the ‘W/R#’ signal is in a logic high level, it means a period for performing a write operation.
In the period for performing a read operation, a clock CLK is enabled after a first time 202. The address counter 130 counts the bank address BADD at a rising edge of the clock CLK. The address counter 130 also counts the first address ADD1<0:A> at a rising edge 203 of the bank address BADD, and the address counter 130 counts the second address ADD2<0:A> at a falling edge 204 of the bank address BADD. Here, the clock CLK is generated by inverting a source clock SCLK and enabling the clock CLK for a designated duration.
The clock CLK is disabled in response to the command latch enable (CLE) signal and the address latch enable (ALE) signal being set to a low logic level at a latch disable time 205, and the counting operation of the bank address BADD, the first address ADD1<0:A>, and the second address ADD2<0:A> are ended.
FIG. 2 shows an operation when the initial bank address BADD_INT is ‘0’ and the column address ADD_INT<0:A> is ‘10001’. The initial bank address BADD_INT begins from ‘0’ and toggles between ‘0’ and ‘1’. The first address ADD1<0:A> and the second address ADD2<0:A> are counted from ‘10001’ to ‘10100’.
As the operation rate of a non-volatile memory device becomes faster, it becomes important to rapidly output data from the page buffers. If data is pre-stored in the pipe latch, fast output operations may be performed.
The value of the bank address BADD has to be the same as the initial bank address BADD_INT at the first time 202. If the value of the bank address BADD is different from the initial bank address BADD_INT at the first time 202, the order of outputting data being outputted from the pipe latch to the input/output pad becomes different.
However, when one period of a clock CLK is longer than ‘tWRCK’, which is a value based on the ONFI specification, a rising edge of the clock CLK appears once in a ‘tWRCK’ period. Thus, the bank address BADD is toggled once and the value of the bank address BADD becomes different from the initial bank address BADD INT.
Therefore, according to the conventional technology, the bank address BADD cannot be counted before the first time 202 and the first address ADD1<0:A> and the second address ADD2<0:A>, which are counted at the rising and falling edges of the bank address BADD, cannot be counted either. As a result, data cannot be stored in the pipe latch before the first time Thus, an error may occur during a high-speed operation.
Herein, ‘tWRCK’ means the time from the first rising edge of the source clock SCLK after the ‘W/R#’ signal transitions to a logic low level to the first rising edge of the source clock SCLK after the command latch enable (CLE) signal and the address latch enable (ALE) signal transition to a logic high level.